verilog port assignment

• The Verilog-AMS Language

Ports, also referred to as pins or terminals, are used when wiring the module to other modules. As such, ports are wires. Ports declarations for simple wire are wire declarations with the keyword wire replaced by one of the following direction specifiers: input , output , or inout . For example:

For other types of wires, or for registers (registers may only be declared as outputs), the declaration is simply preceded by the direction specifier:

By default the content of multi-bit ports are interpreted as unsigned numbers (the values are interpreted as positive binary numbers). It is possible to explicitly specify whether the number is to be interpreted as a signed or unsigned number as follows:

In this case, gain is unsigned and offset is signed, which means it is interpreted as a twos-complement signed number. So, if gain = 4’bF, its value is interpreted as 15, and if offset = 7’b7FF, then its value is interpreted as -1.

If it is necessary to apply a discipline to a port, the port declaration should be repeated with direction specifier replaced by the discipline. For example:

Verilog also supports buses of continuous signals and wreals (you must declare these as buses rather than arrays):

The Cadence simulator does not seem to follow the standard when it comes to declaring buses of wreals. With the Cadence simulator you should declare buses of wreals as arrays rather than as buses:

Modules and Ports in Verilog

An interface to communicate with other modules or a testbench environment is called a port. In simple words, the input/ output pins of digital design are known as ports. This interface is termed a port interface or port list. Since the port list is available for connection, internal design implementation can be hidden from other modules or an environment.

Connection rules in Verilog port

While writing a module, the designer needs to make sure what type of signals have to be connected to the module’s inputs and outputs and follow the below rules.

Module instantiation

Method a: connecting a port list in an ordered manner.

An ordered manner connection is feasible when a port list has minimum signals as the user has to follow the same order in which design level signals are declared.

Method B: Connecting a port list by name

Assign Statement In Verilog

• You can use assign statement inside of module.
• You can use assign statement to output port and any wire declared inside the module

Examples of assign statement

In above example, y is output port and we are assigning this output port to a and b. It will create a and gate where a and b are inputs and y is output

In above example, we've descrived a NAND gate. We can use one statemetn but for better understanding we've use two statement to illustrate how we can use assign statement to both wire and output port. wire w is assign with a AND b, and output y is assigned not of wire w. This creates a NAND gate in verilog HDL.

In above example, we have described a full-adder using assign statement. Note that we can write complete boolean equation using assign statement

We can also use Verilog operators using assign statement. Below is the example of full-adder using assign statement and Verilog operator

In above example, we are using + operator, which addition operator in Verilog. We are assigning output sum and carry with addition of a, b and cin.

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Verilog Ports

In the previous article we covered how a block for a digital design can be defined in the Verilog using module … endmodule keywords. Let’s now move to the next part to see how we can define ports (inputs and outputs) in Verilog.

Verilog Ports Syntax

Verilog ports declaration provides the mechanism to define the signals as inputs and outputs. Syntax provided by the Verilog for ports declaration is as follows;

So for defining Verilog ports, we need four parameters which are as follows;

• Direction of the port
• Size of the port
• Type of the port
• Name of the port

Port Direction

Direction of the port defines whether the signal we intend to use as the port is the input to the module or going out of the module as the output. input and output keywords are used to define a signal as the input and output port respectively. 

Port’s Data Type

Second field in port declaration is the data type of the port. Though Verilog provides a number of data types, only a few of them that are synthesizable and can be used for hardware design. Most commonly used data types are wire and reg type. reg is used for the signals for which we intend to store the data or their values are updated on the occurrence of some event thereby keeping the previous value retained for that length of time. While the wire type signals update their values instantly as soon as their input source changes its value.

The behaviour of this data type is almost similar to the wire used in actual hardwire in which we can store the current and it changes as soon as its input source changes its value. If we do not provide any data type for the port, it will by default be taken as wire .

Next part is the size of the port which defines how many bits of data will this port be carrying. The port size is defined using the square brackets [ ] e.g [ 7:0] . It means that the signal is a 8 bits port with bits from 7 down to 0. We can also define the port size in a more compact way using a number inside the square bracket. This number defines the size of the port in bits e.g [8] , it means that the signal is of 8 bits. So from the above discussion, [7:0] and [8] both define a port size of 8 bits. If you leave the size field blank, it defaults to 1 bit.

In the last part of the port declaration, we assign a name to the port. It is a recommended practice to have a meaningful name for the signal which depends upon its functionality. So continuing the example of AND design using Verilog, we can now define the ports for it. It has two 1-bit inputs and a 1-bit output. So now we have three signals on the port which are defined in terms of their fields as follows;

 Table for AND gate Ports

Here we can see that if we do not provide any size of the ports, it by default is 1 bit. Similarly the wire is the default data type. So now combining the port declaration with block or module definition, we get the external part of our digital design.

As we have covered the first two components of the digital design i.e block or module definition and ports declaration, from the next article we will move to the logic part and what features Verilog provide for logic building.

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Verilog Assignments

Variable declaration assignment, net declaration assignment, assign deassign, force release.

• Procedural continuous

Legal LHS values

An assignment has two parts - right-hand side (RHS) and left-hand side (LHS) with an equal symbol (=) or a less than-equal symbol (<=) in between.

The RHS can contain any expression that evaluates to a final value while the LHS indicates a net or a variable to which the value in RHS is being assigned.

Procedural Assignment

Procedural assignments occur within procedures such as always , initial , task and functions and are used to place values onto variables. The variable will hold the value until the next assignment to the same variable.

The value will be placed onto the variable when the simulation executes this statement at some point during simulation time. This can be controlled and modified the way we want by the use of control flow statements such as if-else-if , case statement and looping mechanisms.

An initial value can be placed onto a variable at the time of its declaration as shown next. The assignment does not have a duration and holds the value until the next assignment to the same variable happens. Note that variable declaration assignments to an array are not allowed.

If the variable is initialized during declaration and at time 0 in an initial block as shown below, the order of evaluation is not guaranteed, and hence can have either 8'h05 or 8'hee.

Procedural blocks and assignments will be covered in more detail in a later section.

Continuous Assignment

This is used to assign values onto scalar and vector nets and happens whenever there is a change in the RHS. It provides a way to model combinational logic without specifying an interconnection of gates and makes it easier to drive the net with logical expressions.

Whenever b or c changes its value, then the whole expression in RHS will be evaluated and a will be updated with the new value.

This allows us to place a continuous assignment on the same statement that declares the net. Note that because a net can be declared only once, only one declaration assignment is possible for a net.

Procedural Continuous Assignment

• assign ... deassign
• force ... release

This will override all procedural assignments to a variable and is deactivated by using the same signal with deassign . The value of the variable will remain same until the variable gets a new value through a procedural or procedural continuous assignment. The LHS of an assign statement cannot be a bit-select, part-select or an array reference but can be a variable or a concatenation of variables.

These are similar to the assign - deassign statements but can also be applied to nets and variables. The LHS can be a bit-select of a net, part-select of a net, variable or a net but cannot be the reference to an array and bit/part select of a variable. The force statment will override all other assignments made to the variable until it is released using the release keyword.

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What is supposed to happen in Verilog if a signal of one width is assigned to another signal of a different width?

As in these two cases:

What should A and D look like in terms of C and B respectively?

• \$\begingroup\$ it ought to spit at you both times, as you clearly don't know what you're doing. I've only ever been nice to it and assigned equal sized things. It might try and guess, or align LSB, I wait with bated breath for the answer. \$\endgroup\$ –  Neil_UK Commented Jan 25, 2017 at 14:10
• \$\begingroup\$ Knowing this information is invaluable when debugging simulations. Obviously I don't intentionally code this way, but it'd be really convenient to know the convention so that I can recognize it when I accidentally have coded a mismatch. \$\endgroup\$ –  user2600959 Commented Jan 25, 2017 at 14:15

Verilog's rules are:

• if you copy a narrower value into a wider target, it is zero-extended (zero MSBs added to the left), or sign-extended into the target. Whether it is zero or sign-extended is determined by the signedness of the right-hand-side expression.
• if you copy a wider value to a narrower target, it gets truncated (MSBs removed on the left).

So it means, in your case:

Note that most synthesis tools will issue a warning in these cases. And they should because it's then unclear you're doing things correctly.

• \$\begingroup\$ I was wondering this for simulation, as the simulator didn't issue warnings. If I had tried synthesis then I am sure it would have. Thank you for the help! \$\endgroup\$ –  user2600959 Commented Jan 25, 2017 at 14:18
• \$\begingroup\$ Indeed, pure simulators may not show warnings, because they care more about pure Verilog's specifications than whether your code is meaningful. You'll see that synthesis tools may potentially leverage a lot of things that simulations tools don't. \$\endgroup\$ –  dim Commented Jan 25, 2017 at 14:24

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therajnish143/Working-RAM-and-ROM-using-verilog

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Working-ram-and-rom-using-verilog, the single port ram.

The Dual Port RAM

Results and Discussions

Single-port ram module.

Inputs : ( data [7:0] 8-bit input data. addr [5:0] 6-bit address. en: Write enable signal. clk: Clock signal. ) Outputs: ( q [7:0]: 8-bit output data.) Behavior: ● Data is written to the RAM at the specified address on the rising clock edge if en is asserted. ● If en is not asserted, the address is stored in addr_reg . ● Output q is assigned the value from the RAM at the address stored in addr_reg . Simulation Flow: ● Generates a clock with a 10-time unit period. ● Applies test vectors at specific time points. ● Creates a VCD file for waveform simulation. ● Stops simulation after 90 time units. Simulation Results: ● The testbench aims to verify the correctness of the single-port RAM module by simulating various scenarios, including write and read operations. ● The waveform simulation results can be analyzed in the generated VCD file ( dump.vcd )

Dual-Port RAM Module

Inputs: (data_a [7:0] and data_b [7:0]: Input data for Port A and Port B. addr_a [5:0] and addr_b [5:0]`: Address for Port A and Port B.

en_a and en_b : Write enable for Port A and Port B. clk : Clock signal ) **Outputs: **(q_a [7:0] and q_b [7:0]: Output data at Port A and Port B.) Behavior: ● On the rising edge of the clock ( posedge clk ): ● If en_a is asserted, write data_a to the RAM at address addr_a . ● If en_a is not asserted, assign q_a the value from the RAM at address addr_a . ● Similarly for Port B ( en_b , data_b , addr_b , and q_b ). Testbench Inputs : (data_a [7:0] and data_b [7:0]: Testbench input data. addr_a [5:0] and addr_b [5:0]: Testbench address for Port A and Port B. we_a and we_b: Testbench write enable for Port A and Port B. clk: Testbench clock.) Testbench Outputs: ( q_a [7:0] and q_b [7:0]: Testbench output data at Port A and Port B.) Testbench Simulation Flow: ● Set initial values for inputs (data_a, addr_a, we_a, data_b, addr_b, we_b). ● Apply test vectors at specific time points. ● Stop the simulation after 40 time units. Test Vector Details: ● Write data to Port A and Port B at different addresses with write enable control. ● Modify and read data from different addresses for Port A and Port B

Inputs: (clk: Clock signal, en: Enable signal , addr [3:0] : 4-bit address.) Outputs: (q [3:0] : 4-bit output data. ) Behavior: ● On the rising edge of the clock ( posedge clk ), if en is asserted, output q is assigned the value from memory at the specified address ( addr ). ● If en is not asserted, output q is set to an undefined value ( 4'bxxxx ). Initial Block: - Initializes the memory with specific 4-bit values at 16 different locations. Testbench Inputs: ( clk : Testbench clock. - en : Testbench enable. - addr [3:0] : Testbench address.) Testbench Outputs: - ( data [3:0] : Testbench output data.) Testbench Initial Blocks: ● $dumpfile and $dumpvars are used to create a VCD file for waveform simulation. - A clock ( clk`) is generated with a period of 10 time units.

● Test vectors are applied to the ROM inputs ( en , addr ) at specific time points. ● The simulation is stopped after 80 time units using $stop . Testbench Simulation Flow: ● Set initial values for inputs ( en , addr ). ● Apply test vectors at specific time points. ● Stop the simulation after 80 time units. Test Vector Details: ● Enable ( en ) and disable ( en=0 ) ROM output at specific addresses. - Change the address ( addr ) to observe different data outputs. ● Set an undefined address ( addr = 4'bxxxx ) to observe an undefined output. Simulation Results: ● The testbench aims to verify the correctness of the ROM module by simulating various scenarios, including enabling/disabling output and reading data from different addresses. ● The waveform simulation results can be analyzed in the generated VCD file ( dump.vcd ).

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Output port continuous assignment problem

I have the code below, which is an array of shift registers connected to each other.

i.e., Sin->sr1->sr2->...sr14->sr15->sr16->Sout.

I got some errors (below) when trying to compile. I have declared the ports as wires, but I still have the same problem. Could you help solve the errors as I can't seem to see the issue?

You declared the signal as:

When you plug in the parameter values, this resolves to:

This is an array of 4 elements (0 to 3), each of which is 4 bits wide.

The problem is this line inside the for loops:

When i is set to its maximum value of 3 in the loop, i+1 is 4, which resolves to:

But, there is no shift_reg[4] element of the array. That explains the warning message. You are selecting an element which is not in the array ("out of bounds").

I don't understand the error message, but I suspect it will go away if you fix the code that produces the warning.

• yes, thanks, I tried [i] instead of [i+1] and it went without errors/warnings. The warning should have been the error :) –  temp1445 Commented Oct 30, 2022 at 11:13

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